Allowed cell rate reciprocal approximation in rate-based available bit rate schedulers

ABSTRACT

A method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a characteristic transmission rate that is related to the system clock frequency ƒ and an allowed cell rate ACR expressed as a floating point number having a mantissa m, and an exponent e, where 0≦m≦511, 0≦e≦31 and ACR=(1+m/512)*2 e . If m≧128 then the reciprocal of the mantissa portion (1+m/512) is evaluated by piece-wise linear approximation of the function: ##EQU1## Otherwise, if m&lt;128 then the mantissa portion is evaluated by piece-wise linear approximation of the function: ##EQU2## A selected cell is then scheduled for transmission at a time T relative to the transmission time T 0  of a cell transmitted immediately prior to the selected cell, where T=T 0  +(ACR -1 )*f. A hardware embodiment of the invention, requiring only one 9-bit two&#39;s complementer, three 11-bit adders, and glue logic for multiplexing/control is easily implemented using VLSI circuitry in compliance with ATM Forum traffic management standards, without resort to hardware division or multiplication.

FIELD OF THE INVENTION

This application is directed to a novel circuit for computing the reciprocal ACR⁻¹ of an Allowed Cell Rate (ACR). ACR⁻¹ is an important parameter in the design of an Asynchronous Transfer Mode (ATM) network incorporating Available Bit Rate (ABR) service.

BACKGROUND OF THE INVENTION

The term ACR is usually expressed as a floating point number (9-bit mantissa and 5-bit exponent) as defined by the ATM Forum. The reciprocal of ACR is of significant importance in the design of an ABR scheduler. The present invention applies the binomial theorem and quadratic approximation techniques to derive equations which are easily implemented in hardware without requiring division or multiplication. Accuracy in excess of 99% is attained for an 11-bit mantissa representation.

SUMMARY OF THE INVENTION

In accordance with the preferred embodiment, the invention provides a method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a given transmission rate that is related to the system clock frequency ƒ and an allowed cell rate ACR expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511 and 0≦e≦31 such that ACR=(1+m/512)*2^(e). The reciprocal of ACR is then given as ACR⁻¹ =1/(1+m/512)*2^(-e). Observe that the negative exponent can be calculated implicitly and hence the problem reduces to evaluating the reciprocal of the mantissa portion: 1/(1+m/512). If m≧128 then such portion is evaluated by piece-wise linear approximation of the function: ##EQU3## Otherwise, if m≦128 then the reciprocal of the mantissa portion is evaluated by piece-wise linear approximation of the function: ##EQU4## A selected cell is then scheduled for transmission at a time T relative to the transmission time To of a cell transmitted immediately prior to the selected cell, where

    T=T.sub.0 +(ACR.sup.-1)*ƒ.

The invention further provides apparatus for approximating the reciprocal ACR⁻¹ of an allowed cell rate ACR expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511 and 0≦e≦31 such that ACR=(1+m/512)*2^(e). The apparatus incorporates a two's complementer for receiving a binary representation of the mantissa m and for producing a two's complement representation thereof, a first adder for receiving first and second binary representations of selected functions of the two's complement representation of the mantissa m and for producing a first binary summation representation thereof, a second adder for receiving third and fourth binary representations of selected constants or selected functions of the two's complement representation of the mantissa m and for producing a second binary summation representation thereof, and a third adder for determining the reciprocal ACR⁻¹ as a binary summation representation of the first and second summation representations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 schematically shows an Allowed Cell Rate (ACR) expressed as a 14-bit floating point number packed in a 16-bit word.

FIG. 2 is a graphical representation of ideal (solid line) and approximated (dashed line) values of ACR⁻¹, with 1/(1+m/512) plotted as the ordinate and m plotted as the abscissa.

FIG. 3 is another graphical representation of ideal (dotted line) and approximated (dashed line) values of ACR⁻¹, with 1/(1+m/512) plotted as the ordinate and m plotted as the abscissa.

FIG. 4 depicts linear approximation of a quadratic function ƒ (a) over three ranges.

FIG. 5 is another graphical representation of ideal (dotted line) and approximated (dashed line) values of ACR⁻, with 1/(1+m/512) plotted as the ordinate and m plotted as the abscissa.

FIG. 6 is a graphical representation of an error function comparison of the ideal and approximated values plotted in FIG. 5.

FIG. 7 is a graphical representation of ideal (dotted line), mathematical model-rendered (dashed line) and hardware model-rendered (solid line) values of ACR⁻¹, with 1/(1+m/512) plotted as the ordinate and m plotted as the abscissa.

FIG. 8 is a graphical representation of percentage error in the mathematical model-rendered values plotted in FIG. 7.

FIG. 9 is a graphical representation of percentage error in the hardware model-rendered values plotted in FIG. 7.

FIG. 10 is a block diagram depiction of a hardware unit for determining ACR⁻¹ in accordance with the invention.

FIGS. 11 (a), 11 (b) and 11 (c) respectively depict bit groupings utilized in the hardware unit of FIG. 10 during determination of ACR⁻¹ for values of m, where: 96<m<128; 64<m<96; and, m≦64.

FIGS. 12(a), 12(b) and 12(c) respectively depict bit groupings utilized in the hardware unit of FIG. 10 during determination of ACR⁻¹ for values of m≧128, where: 256<(512-m); 128<(512-m)<256; and, (512-m)≦128.

FIG. 13 tabulates offset adjustments used in refining the mathematical model renderings shown in FIG. 7.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

An ABR scheduler implemented in accordance with the ATM Forum Traffic Management Specification (ATM Forum/94-0849 and 95-0013R8) requires calculation of the reciprocal of ACR in order to schedule a cell belonging to a particular Virtual Circuit (VC) in the next available time slot. The parameter ACR is expressed as a 14-bit floating point number given by ##EQU5## where 0≦e≦31, 0≦m≦511 and nz={0,1} are packed in a 16-bit word as shown schematically shown in FIG. 1. Note that if nz=0, then ACR is 0. Otherwise, ACR is a floating point number dictated by the values of m and e. The reciprocal of ACR is given by ##EQU6##

In order to evaluate ACR⁻¹ with a reasonable degree of accuracy, Equation (1) must be analyzed to select an ideal representative length for the reciprocal. If the size of the reciprocal is restricted to 2 bytes, as is practical from an implementation standpoint, then, for maximum efficiency, ACR⁻¹ may be expressed as a floating point number having an 11-bit mantissa and a 5-bit exponent. The fact that the exponent is negative (2^(-e)) is implicitly conveyed.

Mathematical Basis

Instead of using a dedicated floating point division unit to perform brute force calculation of ACR⁻¹, which would be expensive both in terms of hardware cost and evaluation time, an alternative solution is derived by analyzing Equation (I), as will now be discussed.

The binomical theorem can be used to express some fractions as an infinite series. Consider the following expansions: ##EQU7## where Δ<<1. The smaller the value of Δ, the better will be the accuracy. For the problem at hand, ##EQU8## Hence ACR⁻¹ is expressed, using Equation (2), as: ##EQU9## Thus, ACR⁻¹ is bounded from above by Equation (6) and involves the computation of second order terms. Examination of Equation (6) reveals that the function value ƒ ranges from 1 to ##EQU10## as m varies from 0 to 511; and, that as m→511, the error induced by the approximation increases gradually. As is hereinafter explained, Equation (4) can be manipulated to reduce this error for higher values of m.

Analysis

FIG. 2 shows the ideal value of ACR⁻¹ (solid line) and the approximation given by Equation (6) (dashed line). FIG. 2 clearly shows that the approximation deviates considerably with increasing values of m. Preferably, the formula should be modified to accommodate larger values of m in order to reduce the accumulated error. m=128 is a suitable cut-off value, because 128 is a power of 2; and

because the error at m=128 is 0.0125 (or 1.56% deviation from the ideal) which is acceptable. Hence, any value of m>128 will have a larger error. Re-expressing Equation (4), yields: ##EQU11## where m+x=512, and 128≦m≦511. If we set ##EQU12## then ##EQU13## where a and x are defined above.

It can be seen that x, whose range is 1, . . . , 384!, is smaller compared to the denominator 1024 and hence the efficiency improves considerably compared to the previous case. Now, a suitable value for a that will both simplify hardware implementation and reduce the error must be selected.

When x is 384 (its maximum value), a=0.3750 and ##EQU14## The selection ##EQU15## can be easily implemented. In essence, Equation (9) becomes ##EQU16## and as a result, we have ##EQU17## FIG. 3 graphically represents the approximation given by Equation (12) (dashed line) and the ideal value (dotted line). The maximum absolute error is 0.0122 yielding a relative error of 1.5262% at m=127, while the root mean square error is 0.00385.

The main disadvantage of the foregoing technique, in terms of implementation complexity, is that multiplication (which is both expensive and slow, from a hardware standpoint) is required to evaluate the second order terms (viz., x² and m²) Secondly, the approximation does not truly upperbound the ideal over the entire range, because Equation (12) has been truncated by using a multiplication factor of 1.5 instead of 1.6 for x=384 for the quadratic term. This fact is exemplified in FIG. 3 near the m=128 region where the approximation is smaller in magnitude than the ideal. As will now be explained, these disadvantages can be overcome by using a piece-wise linear approximation model.

Piece-wise Linear Approximation

As is well known, a non-linear function ƒ(a), can be represented as a linear function over an infinitesimal interval Δ. Thus, the quadratic function ƒ(a)=a², may be represented as a sequence of linear approximations in order to simplify hardware computation and reduce the relative error.

Three ranges are used to approximate ƒ(a) for a= 0, . . . , 0.375!. The partitions for each range are selected to be a fractional power of 2 (or a combination that can be represented in fractional powers of 2) in order to avoid a requirement to perform division or multiplication. ##EQU18##

FIG. 4 graphically illustrates the use of three straight lines to approximate the quadratic function for the defined range. Note that the function value of the approximation is never less than the quadratic function's value. The maximum difference occurs exactly at the mid point of each range (e.g.. a=1/16 for Range 1) while the minimum difference (of 0) occurs at the boundary points.

The above model can be adapted to the problem at hand, viz., to evaluate Equation (12). Observe that the range of a adequately covers both partitions i.e. for m≧128, we have ##EQU19## and when m≦127, we have ##EQU20## Hence, the formula for computing the reciprocal becomes: ##EQU21##

FIG. 5 graphically depicts the approximation yielded by Equation (16) 2 0 (dashed lines) and also shows the ideal value (dotted lines). Note that the approximation lies above the ideal case for all values of m≦511. The maximum error is 0.0124687 at m=127, while the relative error is 1.556%. A plot of the error function is shown in FIG. 6.

The performance can be further refined by subtracting specific constants or offsets at the boundary points. The selected constants should be easily represented for a given bit-length and should be amenable to hardware implementation. The offsets tabulated in FIG. 13 were derived through numerical analysis of specific points and were converted to the nearest fractional representation (up to a 12-bit precision) wherever possible by considering their minimum values for the specified range, and were then integrated into Equation (16) by suitable mathematical manipulation. The main criteria used in selecting offsets are that the resultant function value should never be smaller than the ideal case, and that they should be amenable to easy hardware implementation.

The final formula incorporating the FIG. 13 offsets is given by: ##EQU22##

FIG. 7 graphically depicts (dashed line) the approximation of the reciprocal rendered by Equation (17), taking into account the offsets described above.

FIG. 7 also graphically depicts (solid line) the reciprocal value yielded by the hardware model described below. FIGS. 8 and 9 respectively depict the variation in error for the Equation (17) approximation and for the hardware model. Note that the hardware model is limited by the accuracy of the bit-representation selected (say 11-bits) as opposed to the potentially higher precision of a software model. However, the maximum error for the hardware model is only 0.007504 and the error relative to the ideal value is 0.9099% which is an improvement compared to the previous case.

Implementation

If it is assumed that the precision is limited to 11 bits, multiplication of Equation (17) by 2048 (i.e. 2¹¹) eliminates most of the denominator terms and simplifies evaluation. The remaining fractional portions can be rounded/truncated to obtain a reasonable degree of accuracy.

FIG. 10 is a block diagram of the preferred hardware embodiment of the invention. The main functional units required for computation of the reciprocal are: one 9-bit two's complementer, three 11-bit adders, and glue logic for multiplexing/control. Latch interfaces may be provided for possible pipeline implementation.

Implementing Equation (16) involves two main partitions on m as discussed previously (Equation (12)): Case I: m<128 and Case II: m≧128; in addition to the calculation of x. Observe that x=512-m for m>0 is equivalent to the two's complement representation of m in 9-bits. Instead of using a subtractor for calculating x=512-m, only its two's complement is needed and therefore a 9-bit inverter/incrementer can be used. The special case m=0 is discussed below.

For each of Cases I and 11, three more checks must be made on m or x to determine the appropriate range as given by Equation (17). Each of these checks will now be discussed in turn, first for Case 1: m<128. ##EQU23## Multiplication by 2048 yields: ##EQU24## The twos complement of -84 is 1964 (as a 11-bit representation). Furthermore m%2 is 1 if m is odd and can be calculated easily by checking the least significant bit (LSB) of m. The bit groupings are shown in FIG. 11(a), where A=4x, B=m, ##EQU25## and D=-84|₁₀ and the summation A+B+C+D is completed in two steps assuming A+B and C+D are executed in parallel as shown in FIG. 10. The carryin bit of the C+D adder is initialized with the LSB of m to round the result when m%2 is 1. ##EQU26## Scaling by 2048 yields: ##EQU27## The bit groupings are shown in FIG. 11(b) and follow the similar pattern explained above in relation to FIG. 11(a). ##EQU28## As before multiplying by 2048 yields ##EQU29## with the bit groupings being shown in FIG. 11(c). Special Case: m=0

When m=0, the reciprocal of ACR is 1. Observe that for the entire range of m i.e. (0≦m≦511), the reciprocal varies between 1≧m>0.5, implying that the most significant bit in the output should always be a `1`. Hence, by clearing all the output bits, one may imply that the reciprocal is 1 in a negative logic (i.e. if m₋₋ out=0 then the reciprocal is 1). This result is implicitly yielded by the computation for m=0, since the two's complement of 0 is 0 and consequently x=0.

Therefore, the output of Case I (c) will be 0 (see Equation (18)).

Case II: m≧128 will now be discussed. ##EQU30## yielding sum 1 while sum2 is initialized to 823. The bit groupings are shown in FIG. 11(c). ##EQU31## Scaling by 2048 yields: ##EQU32## The bit groupings are shown in FIG. 12(b). ##EQU33## The bit groupings are shown in FIG. 12(c).

It can thus be seen that, in general, the invention involves piece-wise linear approximation of equation (12), thereby eliminating the need for multiplication in evaluating quadratic terms. The invention accordingly facilitates scheduling of cell transmission over an asynchronous transfer mode communication channel having a system clock frequency ƒ and an allowed cell rate ACR. A selected cell is scheduled for transmission at a time T relative to the transmission time T₀ of a cell transmitted immediately prior to said selected cell, where

T=T₀ +(ACR⁻¹)* ƒ.

Alternative Implementations

Other possible hardware implementations of the invention include actual hardware division or table-lookup techniques. But, implementation of high speed division requires expensive hardware and usually involves multiplication/array addition. Table look-up techniques may require circuits of comparable or greater complexity than the circuitry required for hardware division. For a Read Only Memory (ROM) implementation, a total of 512×11 -bits=704 bytes is required. The area for such a ROM in the case of a 0.6 micron 5 V, high density CMOS technology implementation is approximately 1400 gates. By comparison, the algorithm proposed above has been coded in VHDL (without pipelining) and the resultant combinational circuit has been synthesized on a 0.6 micron, CMOS library using a logic synthesizer (the VHDL code appears in the attached Appendix). The resultant circuit was analyzed using a static timing analyzer. The statistics of the implementation are summarized below in Table 1.

                  TABLE 1                                                          ______________________________________                                         Area/timing data of the implemented circuit                                    Gate Equivalent   Maximum Delay                                                ______________________________________                                         ˜660 (no timing constraints)                                                               ˜23 ns                                                 ˜890 (with timing constraints)                                                             ˜13 ns                                                 ______________________________________                                    

It can thus be seen that the invention provides a simple, extremely accurate and computationally inexpensive means for computing the reciprocal, without ever yielding a result which exceeds the actual cell rate. The invention can be implemented in a hardware circuit with full parallelism, utilizing only one 9-bit two's complementer and three 11-bit adders with some glue logic. The percentage of error is 0.901% or equivalently the ACR computed from the reciprocal is accurate to 99.108% of the ideal value over the whole dynamic range. The invention is also amenable to pipelining with a speed-up factor of at least 3.

As will be apparent to those skilled in the art in the light of the foregoing disclosure, many alterations and modifications are possible in the practice of this invention without departing from the spirit or scope thereof Accordingly, the scope of the invention is to be construed in accordance with the substance defined by the following claims.

                  APPENDIX                                                         ______________________________________                                         FUNCTION :                                                                      This hardware module approximates the reciprocal of ACR                        when the mantissa is in the range (0 <= m <= 511)                              Specifically, it computes 1/(1+ m/512) using the binomial                      expansion and quadratic approximation techniques                               upto a 11-bit precision.                                                       GENERICS:                                                                      INPUT PORT DESCRIPTION :                                                      m       : a 9-bit mantissa.                                                    OUTPUT PORT DESCRIPTION :                                                      m.sub.-- out                                                                           : the reciprocal of (1+ m/512) as a 11-bit number                      NOTES :                                                                         a) For 1 <= m <= 511, the output, m.sub.-- out                                       is in the range 1 > m.sub.-- out > 0.5.                                 b) For m=0, the output is cleared i.e, m.sub.-- out=0                                 implying that the reciprocal is 1 (negative - -                         logic)                                                                         LIBRARY IEEE;                                                                  LIBRARY compass.sub.-- lib;                                                    USE ieee.std.sub.-- logic.sub.-- 1164.ALL;                                     USE compass.sub.-- lib.compass.ALL;                                            USE compass.sub.-- lib.stdcomp.ALL;                                            ENTITY one.sub.-- by.sub.-- m IS                                               PORT( m  : IN std.sub.-- logic.sub.-- vector(8 DOWNTO 0) :=                                       (OTHERS => `Z`);                                            m.sub.-- out                                                                            : OUT std.sub.-- logic.sub.-- vector(10 DOWNTO 0)                      );                                                                            END one.sub.-- by.sub.-- m;                                                    ARCHITECTURE rtl OF one.sub.-- by.sub.-- m IS                                  CONSTANT width : integer :=11;                                                 BEGIN                                                                          p1:                                                                            PROCESS (m)                                                                        VARIABLE result  : std.sub.-- logic.sub.-- vector(width-1 DOWNTO 0)            :=                                                                                                  (OTHERS                                               =>  `0`);                                                                          VARIABLE sum1 : std.sub.-- logic.sub.-- vector(width-1 DOWNTO 0) :=                                 (OTHERS                                               =>  `0`);                                                                          VARIABLE sum2 : std.sub.-- logic.sub.-- vector(width-1 DOWNTO 0) :=                                 (OTHERS                                               =>  `0`);                                                                      VARIABLE x : std.sub.-- logic.sub.-- vector(8 DOWNTO 0) := (OTHERS             => `0`);                                                                       BEGIN                                                                          x := (NOT(m)) + `1`;                                                           x=512- m is equivalent to the                                                  Two's complement of m in 9-bits                                                               for m >0.                                                       IF (to.sub.-- integer(m) ≧ 128) THEN                                    1024 mode (II part)                                                            IF (to.sub.-- integer(x) > 256) THEN                                           257 <= x <= 384                                                                       result = 1/2 + x/(2*1024) + 9*x/(4*8*1024)                                              -3*268/(4*2048) to                                                    result = 1024 + 2*x + x/8 - 201 which is equivalent                                        to                                                                 result = 823.00 + 2*x + x/8                                             sum1 := (extend(x,10) & `0`) +                                                                 extend(x(8 DOWNTO 3), width);                                  sum2 := to.sub.-- stdlogicvector(823,width);                                   result :=sum1 + sum2 ;                                                         ELSIF (to.sub.-- integer(x) > 128) THEN                                        129 <= x <= 256                                                                       result = 1/2 + x/(2*1024) + 9*x/(4*8*1024) -27/1024                                     + (1/2048)                                                                    if x modulo 2 = 1;                                                     result = 1024 + x + x/2 + x/16 -54 + carryin after                                          decimal pt                                                        result = 970 + x + x/2 + x/16                                           sum1 := extend(x,width) + to.sub.-- stdlogicvector(970,width);                 sum2 := (x & x(0) & x(0)) + extend(x(8 DOWNTO 1), width)                                       + x(0);                                                        result := sum1 + extend(sum2(10 DOWNTO 3), width);                             ELSE                                                                           1 <= x <= 128                                                                         result = 1/2 + x/(2*1024) + 3*x/(4*8*1024) scaled to                            result = 1024 + x/2 + x/8 + x/16                                       sum2 := ("10" & x);                                                            sum1 := (extend(x,10) & `0`) +                                                               extend(x(8 DOWNTO 1), width);                                    result := sum2 + (("0000") & sum1(10 DOWNTO 4)) +                                      (sum1(3) OR sum1(2) OR sum1(1) or sum1(0));                            END IF ;                                                                       ELSE                                                                           512 mode (I part)                                                              IF (to.sub.-- integer(m) > 96) THEN                                                         97 <= m <= 127                                                           result := 1 - m/512 + 3*m/(8*512) - 21/512                                                  (+ 1/2048)                                                              if m modulo 2=1                                                          result := 4*(512 - m) + 3*m/2 -84 + m(0);                               sum1 := (x & "00") + extend(m,width);                                          sum2 := extend(m(8 DOWNTO 1),width) +                                                       to.sub.-- stdlogicvector(1964,width) + m(0);                             1964 refers to 2's complement of 84 in 11-bits                          result := sum1 + sum2;                                                         ELSIF (to.sub.-- integer(m) > 64) THEN                                         65 <= m <= 96                                                                         result := 1 - m/512 + 3*m/(8*512)                                               result := 1 - m/512 + 3*m/(8*512) - 17/512                                     result := 4*(512 - m) + 3*m/2 - 68;                                    sum1 := (x & "00") + extend(m,width);                                          sum2 := extend(m(8 DOWNTO 1),width) +                                                  to.sub.-- stdlogicvector(1980,width) + m(0);                           1980 refers to 2's complement of 68 in 11-bits                                        m(0) is added to for left over fractions                                result := sum1 + sum2;                                                         ELSE                                                                           0 <= m <= 64 case                                                                     result := 1 - m/512 + m/(8*512) which is scaled to                              result := 4*(512 - m) + m/2                                                    result := 4*x + m/2                                                            Note: If m=0, then x (2's comp) is 0,                                          and result=0;                                                                  sum1 := to.sub.-- stdlogicvector(0,width);                                     sum2 := to.sub.-- stdlogicvector(0,width);                             sum1 := (x & "00");                                                            sum2 := extend(m(8 DOWNTO 1),width);                                           result := sum1 + sum2 + m(0);                                                  m(0) is added to account for left over fractions                               to be on the safe side                                                         END IF ;                                                                       END IF;                                                                        m.sub.-- out <= result;                                                        END PROCESS p1;                                                                END rtl;                                                                       ______________________________________                                     

What is claimed is:
 1. A method of scheduling cell transmission over an asynchronous transfer mode communication channel, said channel characterized by a clock frequency ƒ and an allowed cell rate A(R expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511, 0≦e≦31 and ACR=(1+m/512)*2³, said method requiring determination of the reciprocal ACR⁻¹ of said allowed cell rate and comprising the steps of:(a) if m≧128 evaluating the reciprocal of the mantissa portion (1+m/512) by piece-wise linear approximation of the function: ##EQU34## (b) if m<128 evaluating the reciprocal of said mantissa portion by piece-wise linear approximation of the function: ##EQU35## (c) scheduling a selected cell for transmission at a time T relative to the transmission time T₀ of a cell transmitted immediately prior to said selected cell, where

    T=T.sub.0 +(ACR.sup.-1)* f.


2. A method of scheduling cell transmission over an asynchronous transfer mode communication channel, said channel characterized by a clock frequency ƒ and an allowed cell rate ACR expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511, 0≦e≦31 and ACR=(1+m/512)*2³, said method requiring determination of the reciprocal ACR⁻¹ of said allowed cell rate and comprising the steps of:(a) if m=0 setting the mantissa reciprocal portion 1/(1+m/512)=1; (b) if 0<m≦64:(i) deriving sum1=4*(512-m) as an 11 bit binary representation; (ii) deriving sum2=m/2 as an 11 bit binary representation; (iii) deriving sum1+sum2 as an 11 bit binary representation; (iv) setting said mantissa reciprocal portion=1 if sum1+sum2=0 and otherwise setting said mantissa reciprocal portion=sum1+sum2; (c) if 64<m≦96:(i) deriving A=4*(512-m) as an 11 bit binary representation; (ii) deriving B=m as an 11 bit binary representation; (iii) deriving sum1=A+B as an 11 bit binary representation; (iv) deriving C=m/2 as an 11 bit binary representation; (v) deriving D=1980 as an 11 bit binary representation; (vi) deriving sum2=C+D as an 11 bit binary representation; (vii) deriving said mantissa reciprocal portion=sum1+sum2 as an 11 bit binary representation; (d) if 96<m<128:(i) deriving A=4*(512-m) as an 11 bit binary representation; (ii) deriving B=m as an 11 bit binary representation; (iii) deriving sum1=A+B as an 11 bit binary representation; (iv) deriving C=m/2 as an 11 bit binary representation; (v) deriving D=1964 as an 11 bit binary representation; (vi) deriving sum2=C+D as an 11 bit binary representation; (vii) deriving said mantissa reciprocal portion=sum1+sum2 as an 11 bit binary representation; (e) if m≦128 and 257≦(512-m)≦384;(i) deriving A=2*(512-m) as an 11 bit binary representation; (ii) deriving B=(512-m)/8 as an 11 bit binary representation; (iii) deriving sum1=A+B as an 11 bit binary representation; (iv) deriving sum2=823 as an 11 bit binary representation; (v) deriving said mantissa reciprocal portion=sum1+sum2 as an 11 bit binary representation; (f) if m≧128 and (512-m)≦256:(i) deriving A=(512-m)/2+3/8*((512-m) modulo 2) as an 11 bit binary representation; (ii) deriving B=(512-m)/16 as an 11 bit binary representation; (iii) deriving sum1=A+B as an 11 bit binary representation; (iv) deriving C=970 as an 11 bit binary representation; (v) deriving D=(512-m) as an 11 bit binary representation; (vi) deriving sum2=C+D as an 11 bit binary representation; (vi) deriving said mantissa reciprocal portion=sum1+sum2 as an 11 bit binary representation; (g) if m≧128 and 1≦(512-m)≧128:(i) deriving A=(512-m)/8 as an 11 bit binary representation; (ii) deriving B=(512-m)/16 as an 11 bit binary representation; (iii) deriving sum1=A-B as an 11 bit binary representation; (iv) deriving sum2=1024 as an 11 bit binary representation; (v) deriving said mantissa reciprocal portion=sum1+sum2 as an 11 bit binary representation; (h) scheduling a selected cell for transmission at a time T relative to the transmission time T₀ of a cell transmitted immediately prior to said selected cell, where

    T=T.sub.0 +(ACR.sup.-1)*f.


3. A method of scheduling cell transmission over an asynchronous transfer mode communication channel, said channel characterized by a clock frequency ƒ and an allowed cell rate ACR expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511, 0≦e≦31 and ACR=(1+m/512)*2³, said method requiring determination of the reciprocal ACR⁻¹ of said allowed cell rate and comprising the steps of:(a) if m=0 then setting the mantissa reciprocal portion 1/(1+m/512)=1; (b) if 0≦m≦64 then:(i) if the two's complement of m=0 then setting said mantissa reciprocal portion=1; (ii) if the two's complement of m≈0 then setting said mantissa reciprocal portion=4*(512-m)+m/2; (c) if 64<m<96 then setting said mantissa reciprocal portion=4*(512-m)+m+m/2-68; (d) if 96<n<128 then setting said mantissa reciprocal portion=4*(512-m)+m+m/2-84+m%2/2; (e) if m≧128 and 247≦(512-m)≦384 then setting said mantissa reciprocal portion=2*(512-m)+(512-m)/8+823; (f) if m≧128 and 129≦(512-m)≦256 then setting said mantissa reciprocal portion=(512-m/2+3/8*((512-m) mod 2) 4 (512-m)/16+970; (g) if m≧128 and 1≦(512-m)≦128 then setting said mantissa reciprocal portion 1/(1+m/512)=(512-m)+(512-m)/8 (512-m)16+1024; and, (h) scheduling a selected cell for transmission at a time 7 relative to the transmission time T₀ of a cell transmitted immediately prior to said selected cell, where

    T=T.sub.0 +(ACR)*f.


4. Apparatus for approximating the reciprocal ACR⁻¹ of an allowed cell rate ACR in scheduling cell transmission over an asynchronous transfer mode communication channel, said allowed cell rate ACR expressed as a floating point number having a mantissa m and an exponent e, where 0≦m≦511, 0≦e≦31 and ACR=(1+m/512)*2³, said apparatus comprising:(a) a two's complementer for receiving a binary representation of said mantissa in and for producing a two's complement representation thereof; (b) a first adder for receiving first and second binary representations of selected functions of said two's complement representation of said mantissa m and for producing a first binary summation representation thereof; (c) a second adder for receiving third and fourth binary representations of selected constants or selected functions of said two's complement representation of said mantissa 1n and for producing a second binary summation representation thereof; and, (d) a third adder for determining said reciprocal ACR⁻¹ as a binary summation representation of said first and second summation representations.
 5. Apparatus as defined in claim 4, wherein:(a) said floating point number further comprises a nine-bit mantissa and a 5-bit exponent; (b) said two's complementer is a 9-bit two's complementer; and, (c) said first, second and third adders are 11-bit adders. 